1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and more particularly, the present invention relates to voltage level shift circuits used in semiconductor integrated circuits.
A claim of priority is made to Korean Patent Application No. 2003-2112, filed on Jan. 13, 2003, the contents of which are herein incorporated by reference in their entirety.
2. Description of the Related Art
Memory circuits and mixed integrated circuits are known which include embedded analog and digital circuits. Generally, the operating voltage of the analog circuits is greater than that of the digital circuits, and accordingly, a voltage level shift circuit is typically interposed as an interface between the analog and digital circuits.
FIG. 1 shows a conventional voltage level shift circuit. As shown, the voltage level shift circuit is generally comprised of an input part 110 and an output part 120. The input part 110 is supplied with a first power supply voltage VDD1 and a ground voltage VSS, and the output part 120 is supplied with a second power supply voltage VDD2 and the ground voltage VSS. The first power supply voltage VDD1 is lower than the second power supply voltage VDD2. For example, the first power supply voltage VDD1 may be 1.8 V and the second power supply voltage VDD2 may be 3.3 V. The input part 110 includes a first inverter 10 and a second inverter 20. The output part 120 includes PMOS transistors 31 and 32, NMOS transistors 33 and 34, and an inverter 40, which are connected as illustrated in FIG. 1.
When an input signal IN transitions from a logic low level of the ground voltage VSS to a logic high level of the first power supply voltage VDD1, an output node 15 of the inverter 10 goes low and an output node 25 of the inverter 20 becomes a logic high level of the first power supply voltage VDD1. As a result, the PMOS and NMOS transistors 32 and 33 of the output part 120 are turned on, the PMOS and NMOS transistors 31 and 34 are turned off, and an output signal Y of the inverter 40 becomes a logic high level of the second power supply voltage VDD2.
When the input signal IN transitions from a logic high level to a logic low level, the output node 15 of the inverter 10 has the first power supply voltage VDD1 and the output node 25 of the inverter 20 has the ground voltage VSS. As a result, the PMOS and NMOS transistors 32 and 33 of the output part 120 are turned off, the PMOS and NMOS transistors 31 and 34 are turned on, and the output signal Y of the inverter 40 becomes a logic low level of the ground voltage VSS.
In a normal operational mode, as set forth above, the voltage level shift circuit 100 receives an input signal IN of the first power supply voltage VDD1 to output an output signal Y of the second power supply voltage VDD2. However, a problem arises when the first power supply voltage VDD1 or the second power supply voltage VDD2 is interrupted in a power-down mode.
For example, in the case where the first power supply voltage VDD1 is interrupted to reduce power consumption, the output nodes 15 and 25 of the inverters 10 and 20 have indefinite voltage levels. If these indefinite voltages of output nodes 15 and 25 become a value of VSS+Vth (where Vth is the threshold voltage of an NMOS transistor), the NMOS transistors 33 and 34 in the output part 120 are turned on. This causes nodes 35 and 36 of the output part 120 to become low, which in turn causes the PMOS transistors 31 and 32 to be turned on. As a result, leakage current paths indicated by dotted lines in FIG. 1 are formed through the PMOS and NMOS transistors 31 and 33 and through the PMOS and NMOS transistors 32 and 34, respectively.
Furthermore, the voltage of the node 35 is divided by on-resistances of the turned-on transistors 31 and 33. A leakage current path can be created in the inverter 40 if the divided voltage of the node 35 reaches a trip (or switching) voltage of the inverter 40.